The present invention relates to a semiconductor device, and more particularly to an ultra-thin, short-channel metal oxide semiconductor field effect transistor (MOSFET).
In 1965, Dr. Gordon Moore, then Director of Research and Development for Fairchild Semiconductor, made the observation that the number of transistor devices per integrated circuit had been doubling every couple of years since the creation of the first integrated circuits in the late 1950's and that he expected the trend to continue for the foreseeable future. This observation was dubbed “Moore's Law” by the trade press. Now almost 40 years later, despite numerous dire predictions of fundamental obstacles, unrelenting industry efforts towards every-increasing semiconductor density have effectively affirmed Dr. Moore's prophetic observation, and the trend is still expected to continue unabated for the foreseeable future. The process of reducing semiconductor device size to increase integrated circuit density is generally referred to as “scaling”.
Ongoing scaling efforts of semiconductor MOS (Metal-Oxide-Semiconductor) devices not only contribute to higher integrated circuit packing density, but also improve integrated circuit performance. As the scaling process proceeds towards the physical limits of currently available MOS technologies and techniques, new technologies and techniques are developed to further decrease device size and increase device performance. As MOS device size decreases, tremendous challenges arise in the areas of device modeling accuracy and process integration. The latest technologies for fabricating integrated circuits (or ICs) using “silicon on insulator” (or SOI) substrates have propelled semiconductor technology ahead for another generation or two of scaling. These SOI-based technologies accomplish this by balancing more expensive SOI wafer substrates with more advanced lithographic patterning tools and techniques. Integrated MOS devices based on thinner SOI substrates provide fully depleted transistor bodies, effectively eliminating undesirable floating body effects. Accordingly, there is a trend in the semiconductor industry towards ultra-thin MOS devices based upon ever-thinner SOI substrates. Another advantage of using ultra-thin SOI substrates is that they permit the body regions of MOS devices to experience a “strain” condition such that carrier mobility (both electrons and holes) is enhanced. The thinner the silicon layer of the SOI substrate, the greater the strain applied to it by the gate dielectric and buried oxide layer (BOX). A significant drawback of such ultra thin SOI devices is that effective source and drain contact resistance is drastically increased, limiting device performance.
Still, some of the benefits of bulk devices with extremely shallow source/drain junction layers are unavoidable in modern scaled MOS device since this approach tends to minimize the short channel effect, eliminating a major impediment to device performance. As attractive as the benefits of ultra-thin source drain structures may be, shallow junctions on bulk silicon and thin SOI are incompatible with conventional high-conductivity silicide processes. Without the low contact resistance afforded by silicidation in source/drain regions, the resulting contact resistance of the thin junction becomes unworkably large.
One common solution to the problem of high effective contact resistance in shallow source/drain junctions is to increase the source and drain junction thickness (raised source/drain) thereby permitting silicidation of the excess silicon, which in turn significantly reduces effective source/drain contact resistance. One popular approach for achieving this is to fabricate MOS devices using thin SOI wafers in combination with raised source/drain junctions so that junction capacitance is reduced. Such “thin SOI” structures tend to range in thickness from several tenths of a micrometer to over 100 micrometers of thickness. In these MOS structures, the channel is fully depleted. As a result there is no unpredictable floating body effect.
An example of this approach is described in U.S. Pat. No. 6,395,589, issued May 28, 2000 to Bin Yu (hereinafter “YU”), entitled “Fabrication of Fully Depleted Field Effect Transistor with High-k Gate Dielectric in SOI Technology”. In YU, a thin-SOI layer is used to form a fully depleted channel region, where source and drain are elevated using an epitaxial growth process. There are a couple of problems with this technique: (1) YU does not deal with the formation of device isolation structures. Device isolation is critical to such an approach, since improper or ineffective device isolation will lead to source/drain shorting. (2) YU describes the use a Damascene gate process to form the gate of the device, requiring the formation of sidewall spacers inside the gate region. Using this approach, if the gate dimension is scaled to about twice the sidewall dimension, the technique becomes useless. The dimension of the sidewall spacer is on the order of 0.1 micrometers, and today's typical gate dimension is in the same range. With further scaling, however, the formation of sidewall spacers inside of the gate structure becomes unattractive. Although lithographic processes are capable of accurately patterning gate structures in the nanometer range, at such small sizes the relatively coarse dimensional tolerances on the sidewall spacers described in YU become unacceptably large with respect to the gate dimensions.
Another example is described in U.S. Pat. No. 6,506,649, issued Jan. 14, 2003 to Ka Hing Fung et al., entitled “Method for Forming Notch Gate Having Self-Align Raised Source/Drain Structure”, (hereinafter “FUNG”). Like YU, FUNG does not describe any device isolation scheme. In FUNG, a notch-undercutting dimension is a limiting factor on minimum gate dimension. Similar to YU, if the FUNG notch-undercutting dimension is in the range of 0.1 micrometer, then this method is not useful for forming gates whose dimensions are in the nanometer range. This means that control of the final gate dimension will be very poor since sidewall spacer tolerances and notch dimension tolerances are both relatively coarse compared the gate dimension. As the gate dimension is reduced into the nanometer range, the gate dimension tolerance must be tightly controlled. However, the relatively coarse dimensional tolerances on the FUNG sidewall spacer and notch dimensions prevent accurate control of a nanometer-range gate dimension fabricated according the method described in FUNG.
U.S. Pat. No. 4,830,975, issued May 16, 1989 to Bovaird et al, entitled “Method of Manufacturing a PRIMOS Device” (hereinafter “BOVAIRD”) describes an alternative to using an epitaxial growth technique for forming raised source and drain structures in MOS devices. In BOVAIRD, an etching process is used create a recessed channel region, effectively elevating source and drain structures with respect to the channel. Although, BOVAIRD does clearly describe how device isolation structures are formed, a significant drawback of the BOVAIRD technique is that it is not self-aligned. As a result, the BOVAIRD technique is unable to meet the stringent tolerance requirements of today's nanometer-range gates.
Another subtractive but self-aligned method is taught in U.S. Pat. No. 6,060,749, issued May 9, 2000 to Shye-Lin Wu, titled “Ultra-Short Channel Elevated S/D MOSFETS Formed on an Ultra-Thin SOI Substrate” (hereinafter “WU”). WU describes a controlled method for selectively removing a portion of an SOI layer in a channel region. The resulting structure has reduced SOI thickness in its channel region as compared to its source and drain regions. The technique described in WU also permits sidewall spacers to form in self-aligned fashion after the gate is formed. This produces gate and spacers are well-defined and self-aligned to one other. A problem with this approach, however is difficulty in controlling SOI thickness in the channel region. Like YU and FUNG, WU does not teach how device isolation is formed.